The Bosch process is a plasma etch process that has been widely used to fabricate deep vertical (high aspect ratio) features (with depth such as tens to hundreds of micrometers), such as trenches and vias, in the semiconductor industry. The Bosch process comprises cycles of alternating etching steps and deposition steps. Details of the Bosch process can be found in U.S. Pat. No. 5,501,893, which is hereby incorporated by reference. The Bosch process can be carried out in a plasma processing apparatus configured with a high-density plasma source, such as an inductively coupled plasma (ICP) source, in conjunction with a radio frequency (RF) biased substrate electrode. Process gases used in the Bosch process for etching silicon can be sulfur hexafluoride (SF6) in an etching step and octofluorocyclobutane (C4F8) in a deposition step. The process gas used in the etching step and the process gas used in the deposition step are respectively referred to as “etch gas” and “deposition gas” hereinbelow. During an etching step, SF6 facilitates spontaneous and isotropic etching of silicon (Si); during a deposition step, C4F8 facilitates the deposition of a protective polymer layer onto sidewalls as well as bottoms of the etched structures. The Bosch process cyclically alternates between etch and deposition steps enabling deep structures to be defined into a masked silicon substrate. Upon energetic and directional ion bombardment, which is present in the etching steps, any polymer film coated in the bottoms of etched structures from the previous deposition step will be removed to expose the silicon surface for further etching. The polymer film on the sidewall will remain because it is not subjected to direct ion bombardment, thereby, inhibiting lateral etching.
One limitation of the Bosch process is roughened sidewalls of etched deep features. This limitation is due to the periodic etch/deposition scheme used in the Bosch process and is known in the art as sidewall “scalloping”. For many device applications, it is desirable to minimize this sidewall roughness or scalloping. The extent of scalloping is typically measured as a scallop length and depth. The scallop length is the peak-to-peak distance of the sidewall roughness and is directly correlated to the etch depth achieved during a single etch cycle. The scallop depth is the peak to valley distance of sidewall roughness and is correlated to the degree of anisotropy of an individual etching step. The extent of scallop formation can be minimized by shortening the duration of each etch/deposition step (i.e. shorter etch/deposition steps repeated at a higher frequency).
In addition to smoother feature sidewalls it is also desirable to achieve a higher overall etch rate. The overall etch rate is defined as a total depth etched in a process divided by a total duration of the process. The overall etch rate can be increased by increasing efficiency within a process step (i.e. decreasing dead time).
In a conventional plasma processing apparatus, a substrate is supported on a substrate support in a processing chamber and the substrate can be a semiconductor wafer having diameters such as 4″, 6″, 8″, 12″, etc. The substrate support may comprise, for example, a radio frequency (RF) powered electrode supported from a lower endwall of the chamber or may be cantilevered, e.g., extending from a sidewall of the chamber. The substrate may be clamped to the electrode either mechanically or electrostatically. The substrate is processed in the processing chamber by energizing a process gas in the processing chamber into a high density plasma. A source of energy maintains a high density (e.g., 1011-1012 ions/cm3) plasma in the chamber, for example, an antenna, such as the planar multiturn spiral coil or an antenna having another shape, powered by a suitable RF source and suitable RF impedance matching circuitry inductively couples RF energy into the chamber to generate a high density plasma. The RF power applied to the antenna can be varied according to different process gases used in the chamber (e.g. etch gas containing SF6 and deposition gas containing C4F8). The chamber may include a suitable vacuum pumping apparatus for maintaining the interior of the chamber at a desired pressure (e.g., below 5 Torr, preferably 1-100 mTorr). A dielectric window, such as the planar dielectric window of uniform thickness or a non-planar dielectric window (not shown) is provided between the antenna and the interior of the processing chamber and forms a vacuum wall at the top of the processing chamber. A gas delivery system can be used to supply process gases into the chamber. Details of such a plasma processing apparatus are disclosed in commonly-owned U.S. Patent Application Publication Nos. 2001/0010257, 2003/0070620, U.S. Pat. No. 6,013,155, or U.S. Pat. No. 6,270,862, each of which is incorporated herein by reference in its entirety.
Gas delivery systems designed for fast gas switching are disclosed in commonly-owned U.S. Pat. Nos. 7,459,100 and 7,708,859 and U.S. Patent Publication Nos. 2007/0158025 and 2007/0066038, the disclosures of which are hereby incorporated by reference.
The substrate preferably comprises a silicon material such as a silicon wafer and/or polysilicon. Various features such as holes, vias and/or trenches are to be etched into the silicon material. A patterned masking layer (e.g. photoresist, silicon oxide, and/or silicon nitride) having an opening pattern for etching desired features is disposed on the substrate.
U.S. Patent Publication No. 2009/0242512 discloses an example of a multi-step Bosch type process in which the chamber pressure is at 35 mTorr for 5 seconds during deposition of a passivation film, 20 mTorr for 1.5 seconds during a low pressure etch step and 325 mTorr for 7.5 seconds during a high pressure etch step (see Table 4.2.1) or 35 mTorr for 5 seconds during deposition, 20 mTorr for 1.5 seconds during low pressure etch, 325 mTorr for 7.5 seconds during high pressure etch and 15 mTorr for 1 second during low pressure etch (see Table 4.2.2). Commonly-assigned U.S. Patent Publication 2011/0244686 discloses a process of etching silicon vias (TSVs) and silicon deep trenches using a 2300 Syndion™ plasma processing system to perform a gas modulated cyclical etch step.
Variation in chamber pressure is desired in other processes such as atomic layer deposition, plasma enhanced CVD, multi-step processes of plasma etching openings in mask material and removal of the mask material, multi-step plasma etch processes wherein the concentration of etchant gas is periodically varied or different layers of material are sequentially etched. To reduce the overall processing time, reduction in the transition period between high and low pressure phases of such cyclical processes would be desirable. For instance, U.S. Patent Publication No. 2009/0325386 discloses a conductance limiting element for rapid adjustment of pressure in a low volume vacuum chamber on the order of tens of milliseconds. The '386 publication states that during processing, a single chemical species can be flowed in the processing region during multiple pressure cycles or different chemical species can be introduced during multiple pressure cycles with the time at high or low pressure ranging from 0.1 to 2 seconds.
A limitation of using inductively coupled plasma chambers for rapid alternating processing is that the chamber volume is large and changes in chamber pressure cannot be effected rapidly due to the large chamber volume. Further, it would be desirable to tailor a chamber to a particular processing regime wherein chamber volume and conductance can be varied to achieve desired chamber pressures and gas switching rates.